I'm Kajal Varma.

Software engineer. Student. Learner. Dreamer.

I am a software engineer at Intuit working on performance, scalability, and reliability. Previously, I was a graduate student at Georgia Institute of Technology.

I am interested in software development and computing systems, including operating systems, computer architecture, and networks.

I also enjoy reading and creating art.

Download Resumé (CV)

Georgia Institute of Technology

Master of Science in Computer Science
GPA: 4.0/4.0

Aug 2018 - Dec 2019

Specialization: Computing Systems
Courses completed:

  • Advanced Operating Systems
  • High Performance Computer Architecture
  • Computer Networks
  • Network Security
  • Big Data Systems and Analytics
  • Introduction to Information Security
  • Advanced Software Engineering
  • Data and Visual Analytics
  • Graduate Algorithms
  • Special Problem (independent research)

Birla Institute of Technology and Science, Pilani - K. K. Birla Goa Campus

B.E. (Hons.) Computer Science
CGPA: 8.64 / 10.0

2012 - 2016

Some relevant courses completed:

  • Operating Systems
  • Computer Architecture
  • Data Storage Technologies and Networks
  • Data Structures and Algorithms
  • Database Systems

National Public School, Indiranagar

Grade XII: 97.60 %
Grade X: Percentile 99.9946, CGPA 10.0

1998 - 2012

Central Board of Secondary Education (CBSE)



Predicting Execution Time of CUDA Kernel Using Static Analysis

Gargi Alavani, Kajal Varma, Santonu Sarkar

ISPA 2018

GPU-based parallel applications are becoming complex and long-running which makes it energy inefficient. Anticipating execution time can help the developers to fix inefficient code before running it. We propose an approach to predict the execution time of a GPU kernel without the need of executing it. We build an analytical model to predict the execution time of a GPU kernel by analyzing the intermediate PTX code of a CUDA kernel.

View Publication

DTLB: Deterministic TLB for Tightly Bound Hard Real-time Systems

Kajal Varma, Geeta Patil, Biju Raveendran

VLSID 2017

This paper proposes a novel TLB architecture - Deterministic Translation Lookaside Buffer – to reduce TLB misses, energy consumption and effective per-access time. This is achieved by backing the TLB contents of the executing task to its PCB on preemption, and transferring the PCB contents back to the TLB when the task resumes execution. Experimental results carried out using MemSim, a single clock cycle simulator developed in Java with Swing GUI, show that the DTLB offers on an average 6.74% of dynamic energy savings over a conventional TLB model.

View Publication


Analysis of Cache Replacement Policy using SESC Simulator
Implemented NXLRU (Next to Least Recently Used) cache replacement policy in the SuperESCalar Simulator. Gathered data on branch prediction accuracy and performance in an out-of-order processor. Classified misses as compulsory, conflict, capacity and coherence misses in the cache.
PromotEd - Webpage
Built a visual interface which recommends courses from multiple online course providers based on desired job roles. Used Python for machine learning algorithms, React, and shell scripts to collect data from MOOC APIs.
Pomodoro Time Tracker Web Application
Built the web application front-end for a time-tracker productivity application using React.
MapReduce Infrastructure using gRPC
Implemented a MapReduce simulation in C++ by using gRPC for communication in a distributed service.
vCPU Scheduler and Memory Coordinator for Virtual Machines
Implementation of a scheduler and memory coordinator to dynamically manage resources assigned to each guest OS running on a hypervisor in a virtualized setting in C.
Energy Estimation of High-Performance Computing Applications
Research thesis on prediction of energy consumption of an NVIDIA CUDA kernel through static analysis of compiled PTX code and power modelling of benchmarks on an NVIDIA GPU. Paper published in ISPA 2018.
DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems
Deterministic translation lookaside buffer (DTLB) and cache design and simulation for hard real-time systems, to eliminate inter-task interference and obtain dynamic energy savings. Paper published in IEEE VLSID 2017.
Linux Kernel Mouse Device Driver Implementation
Implementation of a kernel device driver module in C to change the brightness of the screen through mouse clicks.
Deterministic Process-Aware Partitioned Cache for Tightly Bound Hard Real-Time Systems
Worked on a research project in the area of real-time operating systems, proposing a cache memory design that eliminates inter-task interference.
Design of Scheduler and Memory for a Real-Time System
Implemented an Earliest Deadline First Scheduler with Stack Resource Policy (EDF-SRP) in C for process scheduling and memory management in a real-time operating system. Implemented MemSim, a memory simulator GUI in Java with a stack, TLB, and cache, to simulate the memory footprint of the schedule generated by EDF-SRP.
Course Recommendation System
Built a course recommendation website for Georgia Tech using student reviews, performed sentiment analysis on the reviews. Compared user-based and item-based collaborative filtering, and content-based recommendation.
Simulation of Delay Tolerant Networks
Simulated a delay tolerant network using the ONE (Opportunistic Network Environment) simulator, and a TCP-network on NS-3 simulator.
Mobile Edge Computing Packet Scheduling
Added support for simulation of Mobile Edge Computing (MEC) networks in NS-3 by implementing custom C++ modules. Added functionality to configure execution of several experiments in order to easily collect and plot data for research purposes.
Simulation of DiskSim disk scheduling algorithms
DiskSim is a hard disk simulation software used for I/O analysis research. Implemented a Java simulation of two scheduling algorithms - cyclic cylindrical access, and shortest access time first. Collected disk usage data of PC using IOMeter, an I/O subsystem measurement and characterization tool for single and clustered systems, as a study of disk performance.
Phased Cache Design and Implementation
Simulated an eight-way associative cache of 512B size and 16B line size using Verilog in ModelSim Altera. Implemented write back policy and FIFO replacement policy in the cache.
TurboTax Sam
Worked in a team of four to develop a chatbot for HackUtsav 2017, an internal hackathon held at Intuit. The chatbot provides quick and easy answers to customers from within TurboTax Windows. Emerged the winners of the hackathon.
Worked in a team of two in the In24Hrs Hackathon held at Intuit. Built a prototype of an Android application that enables the visually impaired to manage their bills through voice.

Work Experience

Software Engineer 2
Intuit, San Diego CA
Jan 2020 - Present
Software engineer working in the Site Reliability, Performance and Scalability - Production Engineering team.
Teaching Assistant
Network Security
August 2019 - Present
Worked as a TA for CS 6262 Network Security taught by Dr Wenke Lee at Georgia Institute of Technology.
Software Engineer Intern
Intuit, San Diego CA
May 2019 - August 2019
Software engineer intern in the Core Tax Services backend team, Consumer Group.
Teaching Assistant
Network Security
January 2019 - May 2019
Worked as a TA for CS 6262 Network Security taught by Dr Wenke Lee at Georgia Institute of Technology.
Software Engineer 2
Intuit India
February 2018 - August 2018
Software developer in the TurboTax Desktop team, Consumer Tax Group. Working on library framework development and Windows application development.
Software Engineer 1
Intuit India
August 2016 - January 2018
Software developer in the TurboTax Desktop team, Consumer Tax Group. Working on library framework development and Windows application development.
Software Engineer Intern
Intuit India
May 2015 - July 2015
Part of Consumer Tax Group, TurboTax Android team. Worked on Android and web application development.
RailTel Corp of India Ltd
May 2014 - July 2014
Summer internship at RailTel Corporation of India Ltd as a part of BITS Pilani's PS-I (Practice School-I) programme.
Teaching Assistant
Computer Architecture
August 2015 - December 2015
Worked as a TA for Computer Architecture at BITS Pilani - K. K. Birla Goa Campus.
Professional Assistant
Computer Programming
January 2015 - May 2015
Worked as a PA for Computer Programming at BITS Pilani - K. K. Birla Goa Campus.


CG Excellence Award 2018

Engineering Excellence Award - 2018 for the Consumer Group at Intuit.

April 2018 Intuit India

Winner, Intuit HackUtsav 2017

Developed a chat bot, TurboTax Sam, as in-product help for TurboTax Windows.

July 2017 Intuit India

National Cyber Olympiad

All-India Rank 17 and Karnataka Rank 1 in the National Cyber Olympiad.

June 2012 Science Olympiad Foundation

Mridula Scholarship

School topper in the Grade X CBSE Board Exam with a national percentile of 99.9946.

Jan 2011 National Public School


C++ C
Java Python
Git Objective-C
Linux/UNIX Win, Mac


Department of Creative Media

Web Design | Web Development

Mime Club, BITS Goa

Performing Arts | Acting

Art Gallery

Sketches | Paintings

Department of Photography

Editing | Photoshop | Lightroom